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Altera 874 dokumentacji

NO. Symbol elementu Rozmiar pliku Stron Opis dokumentacji Producent
1. 10K 1.92 MB 128 FLEX 10K Embedded Programmable Logic Family Data Sheet Altera
2. 10K 343 KB 8 AN 86: Implementing the pci_a Master/Target in FLEX 10K Devices Altera
3. 10K 449 KB 40 AN 102: Improving Performance in FLEX 10K Devices with Leonardo Spectrum Software Altera
4. 10K 349 KB 24 AN 106: Designing with 2.5-V Devices Altera
5. 10K 399 KB 17 QFP Carrier & Development Socket Data Sheet Altera
6. 10K 61 KB 1 EPF10K100B Embedded Programmable Logic Device Errata Sheet Altera
7. 10K 45 KB 1 EPF10K100E Embedded Programmable Logic Device Errata Sheet Altera
8. 10K 47 KB 1 EPF10K200E Embedded Programmable Logic Device Errata Sheet Altera
9. 10K 236 KB 4 SB 4 Complex Multiplier/Mixer Megafunction Altera
10. 10K 211 KB 4 SB 11: Linear Feedback Shift Register Megafunction Altera
11. 10K 146 KB 3 SB 26: PCI Bus Master/Target Interface Megafunction Altera
12. 20K 183 KB 12 AN 112: Integrating Product-Term Logic in APEX 20K Devices Altera
13. 20K 1.89 MB 76 AN 120: Using the LVDS in APEX 20KE Devices Altera
14. 20K 562 KB 8 APEX Devices Brochure Altera
15. 20K 109 KB 6 Designing Switches & Routers with APEX CAM Altera
16. 20K 615 KB 40 APEX 20KE PCI Starter & Development Kits Data Sheet Altera
17. 20K 91 KB 8 SignalTap Embedded Logic Analyzer Megafunction Data Sheet Altera
18. 20K 92 KB 2 New APEX 20KE Device Ordering Codes Altera
19. 20K 561 KB 20 Using APEX 20K & APEX 20KE PLLs in the Quartus Software Altera
20. 20K 1.50 MB 30 Using LVDS in the Quartus Software Altera
21. 20K 190 KB 6 Board Design Guidelines for LVDS Systems Altera
22. 6000 242 KB 21 AN 92: Understanding FLEX 6000 Timing Altera
23. 6000 1.00 MB 102 AN 116: Configuring SRAM-Based LUT Devices Altera
24. 7000 196 KB 11 AN 85: In-System Programming Times for MAX Devices Altera
25. 7000 253 KB 13 BitBlaster Serial Download Cable Data Sheet Altera
26. 7000 1.17 MB 62 MAX 7000 Programmable Logic Device Family Data Sheet, Altera
27. 7000 1.12 MB 62 MAX 7000B Programmable Logic Device Family Data Sheet Altera
28. 7000 35 KB 2 TB 33: Evaluating MAX 7000S Device Utilization and Fitting Altera
29. ACEX 1.23 MB 86 ACEX 1K Programmable Logic Device Family Data Sheet Altera
30. ACEX 175 KB 4 ACEX Devices Brochure: Low-Cost Solutions for High Volume Applications Altera
31. ACEX 869 KB 32 EPC16 Configuration Device Data Sheet Altera
32. ACEX 69 KB 5 Configuring PLDs with FLASH Memory Altera
33. ACEX 1K 37 KB 4 Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) Altera
34. ACEX 1K 1.00 MB 102 AN 116: Configuring SRAM-Based LUT Devices Altera
35. ACEX 1K 43 KB 4 Figure 43 Design File for Configuring APEX 20K (43 KB) Altera
36. ACEX 1K 410 KB 6 Ordering Information Altera
37. Apex 183 KB 12 AN 112: Integrating Product-Term Logic in APEX 20K Devices Altera
38. Apex 1.89 MB 76 AN 120: Using the LVDS in APEX 20KE Devices Altera
39. Apex 562 KB 8 APEX Devices Brochure Altera
40. Apex 109 KB 6 Designing Switches & Routers with APEX CAM Altera
41. Apex 615 KB 40 APEX 20KE PCI Starter & Development Kits Data Sheet Altera
42. Apex 91 KB 8 SignalTap Embedded Logic Analyzer Megafunction Data Sheet Altera
43. Apex 92 KB 2 New APEX 20KE Device Ordering Codes Altera
44. Apex 561 KB 20 Using APEX 20K & APEX 20KE PLLs in the Quartus Software Altera
45. Apex 1.50 MB 30 Using LVDS in the Quartus Software Altera
46. Apex 190 KB 6 Board Design Guidelines for LVDS Systems Altera
47. Apex 405 KB 8 APEX II Devices Altera
48. Apex 1.21 MB 96 APEX II Programmable Logic Device Family Data Sheets Altera
49. Apex 180 KB 8 MasterBlaster Serial/USB Communications Cable Data Sheets Altera
50. Apex 20K 37 KB 4 Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) Altera
51. Apex 20K 1.00 MB 102 AN 116: Configuring SRAM-Based LUT Devices Altera
52. Apex 20K 43 KB 4 Figure 43 Design File for Configuring APEX 20K (43 KB) Altera
53. Apex 20K 1.53 MB 50 AN 119: Implementing High-Speed Search Applications with Altera CAM Altera
54. Apex 20K 591 KB 56 AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices Altera
55. Apex 20K 229 KB 15 AN 138: LVDS Signaling Using APEX Devices I/O Pins Altera
56. Apex 20K 160 KB 12 AN 107: Using Altera Devices in Multi-Voltage Systems Altera
57. Apex 20K 212 KB 13 AN 114: Designing with FineLine BGA Packages Altera
58. Apex 20K 349 KB 24 AN 106: Designing with 2.5-V Devices Altera
59. Apex 20K 1.35 MB 30 AN 117: Using Selectable I/O Standards in Altera Devices Altera
60. Apex 20K 869 KB 32 EPC16 Configuration Device Data Sheet Altera
61. Apex 20K 69 KB 5 Configuring PLDs with FLASH Memory Altera
62. Apex 20K 1.78 MB 116 APEX 20K Programmable Logic Device Family Data Sheet Altera
63. Apex 20K 1.44 MB 90 APEX 20KC Programmable Logic Device Data Sheet Altera
64. Apex 20K 52 KB 1 EP20K400 Device Altera
65. Apex 20K 186 KB 3 APEX 20KE Programmable Logic Devices Altera
66. Apex 20K 180 KB 8 MasterBlaster Serial/USB Communications Cable Data Sheet Altera
67. Apex 20K 381 KB 28 Configuration Devices for APEX & FLEX Devices Data Sheet Altera
68. Apex 20K 352 KB 16 Quartus Programmable Logic Development System & Software Data Sheet Altera
69. Apex 20K 113 KB 4 TB 56: Using APEX 20KE CAM for Fast Search Applications Altera
70. Apex 20K 190 KB 6 TB 57: Power Consumption Comparison: APEX 20K vs. Virtex Devices Altera
71. Apex 20K 130 KB 4 TB 60: Advantages of APEX PLLs over Virtex DLLs Altera
72. Apex 20K 122 KB 4 TB 61: CAM Comparison: APEX 20KE vs. Virtex-E Devices Altera
73. Apex 20K 1.59 MB 7 TB 70: Jitter Comparison Analysis APEX 20KE PLL vs. Virtex-E DLL Altera
74. Apex 20K 132 KB 8 APEX CAM as Cache for External CAM Altera
75. APEX CAM 109 KB 6 Designing Switches & Routers with APEX CAM White Paper Altera
76. Apex II 37 KB 4 Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) Altera
77. Apex II 1.00 MB 102 AN 116: Configuring SRAM-Based LUT Devices Altera
78. Apex II 1.53 MB 50 AN 119: Implementing High-Speed Search Applications with Altera CAM Altera
79. Apex II 108 KB 10 AN 162: Increasing System Bandwidth with CDS Altera
80. Apex II 515 KB 12 ByteBlasterMV Parallel Port Download Cable Data Sheets Altera
81. Application Brief 144 KB 3 AB 124: Prescaled Counters in FLEX 8000 Devices Altera
82. Application Brief 174 KB 3 AB 130: Parity Generators in FLEX 8000 Devices Altera
83. Application Brief 109 KB 4 AB 131: State Machine Encoding Altera
84. Application Brief 185 KB 4 AB 135: Ripple-Carry Gray Code Counters in FLEX 8000 Devices Altera
85. Application Brief 96 KB 19 AB 143: Understanding FLEX 8000 Timing Altera
86. Application note 37 KB 4 Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) Altera
87. Application note 1.00 MB 102 AN 116: Configuring SRAM-Based LUT Devices Altera
88. Application note 43 KB 4 Figure 43 Design File for Configuring APEX 20K (43 KB) Altera
89. Application note 1.53 MB 50 AN 119: Implementing High-Speed Search Applications with Altera CAM Altera
90. Application note 591 KB 56 AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices Altera
91. Application note 229 KB 15 AN 138: LVDS Signaling Using APEX Devices I/O Pins Altera
92. Application note 160 KB 12 AN 107: Using Altera Devices in Multi-Voltage Systems Altera
93. Application note 212 KB 13 AN 114: Designing with FineLine BGA Packages Altera
94. Application note 349 KB 24 AN 106: Designing with 2.5-V Devices Altera
95. Application note 1.35 MB 30 AN 117: Using Selectable I/O Standards in Altera Devices Altera
96. Application note 108 KB 10 AN 162: Increasing System Bandwidth with CDS Altera
97. Application note 399 KB 39 AN 33: Configuring FLEX 8000 Devices Altera
98. Application note 439 KB 21 AN 38: Configuring Multiple FLEX 8000 Devices Altera
99. Application note 469 KB 24 AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor Altera
100. Application note 299 KB 31 AN 91: Understanding FLEX 10K Timing Altera

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