Producenci
Altera 874 dokumentacji
NO. | Symbol elementu | Rozmiar pliku | Stron | Opis dokumentacji | Producent |
---|---|---|---|---|---|
101. | Application note | 305 KB | 8 | AN 96: Performance Measurements of Typical Applications | Altera |
102. | Application note | 247 KB | 12 | AN 97: Comparing Performance of High-Density PLDs | Altera |
103. | Application note | 127 KB | 4 | AN 99: Comparing Performance of Dual-Port Memory Functions | Altera |
104. | Application note | 738 KB | 56 | AN 101: Improving Performance in FLEX 10K Devices with the Synplify Software | Altera |
105. | Application note | 273 KB | 14 | AN 90: SameFrame Pin-Out Design for FineLine BGA Packages | Altera |
106. | Application note | 325 KB | 29 | AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices | Altera |
107. | Application note | 312 KB | 12 | AN 51: Using Programmable Logic for Gate Array Designs | Altera |
108. | Application note | 202 KB | 24 | AN 73: Implementing FIR Filters in FLEX Devices | Altera |
109. | Application note | 150 KB | 8 | AN 80: Selecting Sockets for Altera Devices | Altera |
110. | Application note | 512 KB | 12 | AN 74: Evaluating Power for Altera Devices | Altera |
111. | Application note | 118 KB | 8 | AN 81: Reflow Soldering Guidelines for Surface-Mount Devices | Altera |
112. | Application note | 224 KB | 11 | AN 36: Designing with FLEX 8000 Devices | Altera |
113. | Application note | 166 KB | 10 | AN 42: Metastability in Altera Devices | Altera |
114. | Application note | 261 KB | 15 | AN 75: High-Speed Board Designs 3.01 | Altera |
115. | Application note | 204 KB | 21 | AN 76: Understanding FLEX 8000 Timing | Altera |
116. | Application note | 237 KB | 18 | AN 77: Understanding MAX 9000 Timing | Altera |
117. | Application note | 227 KB | 15 | AN 78: Understanding MAX 5000 & Classic Timing | Altera |
118. | Application note | 196 KB | 11 | AN 85 In-System Programming Times for MAX Devices | Altera |
119. | Application note | 210 KB | 12 | AN 109: Using the HP 3070 Tester for In-System Programming | Altera |
120. | Application note | 214 KB | 12 | AN 94: Understanding MAX 7000 Timing | Altera |
121. | Application note | 285 KB | 12 | AN 82: Highly Optimized 2-D Convolver | Altera |
122. | Application note | 174 KB | 16 | AN 83: Binary Numbering Systems | Altera |
123. | Application note | 191 KB | 8 | AN 133: QDR SRAM Controller Function | Altera |
124. | Application note | 225 KB | 16 | AN 130: CDR in Mercury Devices | Altera |
125. | Application note | 507 KB | 48 | AN 131: Using General Purpose PLLs in Mercury Devices | Altera |
126. | Application note | 185 KB | 14 | AN 128: Implementing Voice Over Internet Protocol | Altera |
127. | Application note | 174 KB | 12 | AN 132: Implementing Multiprotocol Label Switching with Altera PLDs | Altera |
128. | Application note | 259 KB | 16 | AN 118: Scripting with Tcl in the Quartus Software | Altera |
129. | Application note | 1.54 MB | 36 | AN 123: Using Timing Analysis in the Quartus II Software | Altera |
130. | Application note | 2.40 MB | 36 | AN 161: Using the LogicLock Methodology in the Quartus II Design Software | Altera |
131. | Application note | 195 KB | 14 | AN 43: Designing for MAX 9000 Devices | Altera |
132. | Application note | 195 KB | 14 | AN 43: Designing for MAX 9000 Devices | Altera |
133. | Application note | 168 KB | 8 | AN 45: Configuring FLASHlogic Devices | Altera |
134. | Application note | 168 KB | 8 | AN 45: Configuring FLASHlogic Devices | Altera |
135. | Application note | 165 KB | 8 | AN 49: Implementing CRCCs In Altera Devices | Altera |
136. | Application note | 165 KB | 8 | AN 49: Implementing CRCCs In Altera Devices | Altera |
137. | Application note | 302 KB | 16 | AN 71: Guidelines for Handling J-Lead & QFP Devices | Altera |
138. | Application note | 302 KB | 16 | AN 71: Guidelines for Handling J-Lead & QFP Devices | Altera |
139. | Application note | 453 KB | 27 | AN 88: Using the Jam Language for ISP via an Embedded Processor | Altera |
140. | Application note | 453 KB | 27 | AN 88: Using the Jam Language for ISP via an Embedded Processor | Altera |
141. | Application note | 215 KB | 20 | AN 100: In-System Programmability Guidelines | Altera |
142. | Application note | 215 KB | 20 | AN 100: In-System Programmability Guidelines | Altera |
143. | Application note | 194 KB | 12 | AN 111: Embedded Programming Using the 8051 and Jam Byte-Code | Altera |
144. | Application note | 194 KB | 12 | AN 111: Embedded Programming Using the 8051 and Jam Byte-Code | Altera |
145. | Application note | 1.89 MB | 76 | AN 120: Using the LVDS in APEX 20KE Devices | Altera |
146. | Application note | 1.89 MB | 76 | AN 120: Using the LVDS in APEX 20KE Devices | Altera |
147. | Application note | 509 KB | 34 | AN 134: Using Programmable I/O Standards in Mercury Devices | Altera |
148. | Application note | 509 KB | 34 | AN 134: Using Programmable I/O Standards in Mercury Devices | Altera |
149. | Application note | 67 KB | 7 | AN 168: Getting Started with the LeonardoSpectrum Software | Altera |
150. | Application note | 67 KB | 7 | AN 168: Getting Started with the LeonardoSpectrum Software | Altera |
151. | Brochure | 175 KB | 4 | ACEX Devices | Altera |
152. | Brochure | 562 KB | 8 | APEX Devices | Altera |
153. | Brochure | 405 KB | 8 | APEX II Devices | Altera |
154. | Brochure | 1.67 MB | 12 | Corporate Brochure | Altera |
155. | Brochure | 786 KB | 8 | Quartus II | Altera |
156. | Brochure | 256 KB | 4 | Excalibur | Altera |
157. | Brochure | 444 KB | 8 | Signal Processing IP Megafunctions | Altera |
158. | Configuration | 515 KB | 12 | ByteBlasterMV Parallel Port Download Cable Data Sheet | Altera |
159. | Controllers | 630 KB | 21 | SDR SDRAM Controller White Paper | Altera |
160. | Controllers | 462 KB | 19 | DDR SDRAM Controller White Paper | Altera |
161. | Controllers | 140 KB | 7 | AN NCS018 (A Basic Controller for the CIDR Co-Processor Longest Prefix Match Engine) | Altera |
162. | Data Sheet | 410 KB | 6 | Ordering Information | Altera |
163. | Data Sheet | 869 KB | 32 | EPC16 Configuration Device Data Sheet | Altera |
164. | Data Sheet | 1.78 MB | 116 | APEX 20K Programmable Logic Device Family Data Sheet | Altera |
165. | Data Sheet | 1.44 MB | 90 | APEX 20KC Programmable Logic Device Data Sheet | Altera |
166. | Data Sheet | 52 KB | 1 | EP20K400 Device | Altera |
167. | Data Sheet | 186 KB | 3 | APEX 20KE Programmable Logic Devices | Altera |
168. | Data Sheet | 381 KB | 28 | Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet | Altera |
169. | Data Sheet | 689 KB | 49 | Sharp LHF16J061 Data Sheet | Altera |
170. | Data Sheet | 354 KB | 16 | ByteBlaster Parallel Port Download Cable Data Sheet | Altera |
171. | Data Sheet | 116 KB | 12 | Altera Programming Hardware Data Sheet | Altera |
172. | Data sheet | 267 KB | 16 | ARM-Based Embedded Processor Device Overview Data Sheet | Altera |
173. | Data sheet | 2.69 MB | 8 | Nios Embedded Processor UART Peripheral Data Sheet | Altera |
174. | Data sheet | 265 KB | 16 | MIPS-Based Embedded Processor Device Overview Data Sheet | Altera |
175. | Data sheet | 8.53 MB | 4 | Nios Embedded Processor Parallel I/O Module Data Sheet | Altera |
176. | Data sheet | 2.65 MB | 6 | Nios Embedded Processor Timer Peripheral Data Sheet | Altera |
177. | Data sheet | 1.92 MB | 100 | FLEX 10KE Embedded Programmable Logic Family Data Sheet | Altera |
178. | Data sheet | 253 KB | 13 | Operating Requirements for Altera Devices Data Sheet | Altera |
179. | Data sheet | 283 KB | 16 | a16450 Universal Asynchronous Receiver/Transmitter Data Sheet | Altera |
180. | Data sheet | 243 KB | 8 | a6402 Universal Asynchronous Receiver/Transmitter Data Sheet | Altera |
181. | Data sheet | 270 KB | 22 | a8237 Programmable DMA Controller Data Sheet | Altera |
182. | Data sheet | 339 KB | 21 | a8251 Programmable Communications Interface Data Sheet | Altera |
183. | Data sheet | 379 KB | 16 | FLEX 10KE PCI Development Board Data Sheet | Altera |
184. | Data sheet | 364 KB | 14 | FLEX 10K PCI Prototype Board Data Sheet | Altera |
185. | Data sheet | 1.02 MB | 59 | FLEX 6000 Programmable Logic Device Family Data Sheet | Altera |
186. | Data sheet | 399 KB | 17 | QFP Carrier & Development Socket Data Sheet | Altera |
187. | Data sheet | 412 KB | 16 | EP220 & EP224 Classic EPLDs Data Sheet | Altera |
188. | Data sheet | 492 KB | 18 | EP312 & EP324 Classic EPLDs Data Sheet | Altera |
189. | Data sheet | 1.05 MB | 63 | FLEX 8000 Programmable Logic Device Family Data Sheet | Altera |
190. | Data sheet | 592 KB | 40 | MAX 3000A Programmable Logic Device Family Data Sheet | Altera |
191. | Data sheet | 1.01 MB | 60 | MAX 7000A Programmable Logic Device Family Data Sheet | Altera |
192. | Data sheet | 148 KB | 8 | crc MegaCore Function Parameterized CRC Generator/Checker Data Sheet | Altera |
193. | Data sheet | 201 KB | 11 | 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet | Altera |
194. | Data sheet | 140 KB | 6 | ATM Cell Processor 155 Mbps MegaCore Function (CP155) Data Sheet | Altera |
195. | Data sheet | 92 KB | 6 | ATM Cell Processor 622 Mbps MegaCore Function (CP622) Data Sheet | Altera |
196. | Data sheet | 77 KB | 5 | PPP Packet Processor 155 Mbps MegaCore Function (PP155) Data Sheet | Altera |
197. | Data sheet | 78 KB | 5 | PPP Packet Processor 622 Mbps MegaCore Function (PP622) Data Sheet | Altera |
198. | Data sheet | 90 KB | 6 | SONET STS-1 Framer MegaCore Function (STS1FRM) Data Sheet | Altera |
199. | Data sheet | 164 KB | 7 | SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet | Altera |
200. | Data sheet | 160 KB | 7 | T3 Framer MegaCore Function (T3FRM) Data Sheet | Altera |