Producenci
Altera 874 dokumentacji
NO. | Symbol elementu | Rozmiar pliku | Stron | Opis dokumentacji | Producent |
---|---|---|---|---|---|
1. | 10K |
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128 | FLEX 10K Embedded Programmable Logic Family Data Sheet | Altera |
2. | 10K |
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8 | AN 86: Implementing the pci_a Master/Target in FLEX 10K Devices | Altera |
3. | 10K |
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40 | AN 102: Improving Performance in FLEX 10K Devices with Leonardo Spectrum Software | Altera |
4. | 10K |
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24 | AN 106: Designing with 2.5-V Devices | Altera |
5. | 10K |
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17 | QFP Carrier & Development Socket Data Sheet | Altera |
6. | 10K |
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1 | EPF10K100B Embedded Programmable Logic Device Errata Sheet | Altera |
7. | 10K |
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1 | EPF10K100E Embedded Programmable Logic Device Errata Sheet | Altera |
8. | 10K |
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1 | EPF10K200E Embedded Programmable Logic Device Errata Sheet | Altera |
9. | 10K |
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4 | SB 4 Complex Multiplier/Mixer Megafunction | Altera |
10. | 10K |
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4 | SB 11: Linear Feedback Shift Register Megafunction | Altera |
11. | 10K |
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3 | SB 26: PCI Bus Master/Target Interface Megafunction | Altera |
12. | 20K |
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12 | AN 112: Integrating Product-Term Logic in APEX 20K Devices | Altera |
13. | 20K |
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76 | AN 120: Using the LVDS in APEX 20KE Devices | Altera |
14. | 20K |
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8 | APEX Devices Brochure | Altera |
15. | 20K |
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6 | Designing Switches & Routers with APEX CAM | Altera |
16. | 20K |
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40 | APEX 20KE PCI Starter & Development Kits Data Sheet | Altera |
17. | 20K |
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8 | SignalTap Embedded Logic Analyzer Megafunction Data Sheet | Altera |
18. | 20K |
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2 | New APEX 20KE Device Ordering Codes | Altera |
19. | 20K |
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20 | Using APEX 20K & APEX 20KE PLLs in the Quartus Software | Altera |
20. | 20K |
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30 | Using LVDS in the Quartus Software | Altera |
21. | 20K |
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6 | Board Design Guidelines for LVDS Systems | Altera |
22. | 6000 |
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21 | AN 92: Understanding FLEX 6000 Timing | Altera |
23. | 6000 |
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102 | AN 116: Configuring SRAM-Based LUT Devices | Altera |
24. | 7000 |
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11 | AN 85: In-System Programming Times for MAX Devices | Altera |
25. | 7000 |
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13 | BitBlaster Serial Download Cable Data Sheet | Altera |
26. | 7000 |
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62 | MAX 7000 Programmable Logic Device Family Data Sheet, | Altera |
27. | 7000 |
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62 | MAX 7000B Programmable Logic Device Family Data Sheet | Altera |
28. | 7000 |
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2 | TB 33: Evaluating MAX 7000S Device Utilization and Fitting | Altera |
29. | ACEX |
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86 | ACEX 1K Programmable Logic Device Family Data Sheet | Altera |
30. | ACEX |
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4 | ACEX Devices Brochure: Low-Cost Solutions for High Volume Applications | Altera |
31. | ACEX |
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32 | EPC16 Configuration Device Data Sheet | Altera |
32. | ACEX |
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5 | Configuring PLDs with FLASH Memory | Altera |
33. | ACEX 1K |
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4 | Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) | Altera |
34. | ACEX 1K |
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102 | AN 116: Configuring SRAM-Based LUT Devices | Altera |
35. | ACEX 1K |
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4 | Figure 43 Design File for Configuring APEX 20K (43 KB) | Altera |
36. | ACEX 1K |
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6 | Ordering Information | Altera |
37. | Apex |
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12 | AN 112: Integrating Product-Term Logic in APEX 20K Devices | Altera |
38. | Apex |
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76 | AN 120: Using the LVDS in APEX 20KE Devices | Altera |
39. | Apex |
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8 | APEX Devices Brochure | Altera |
40. | Apex |
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6 | Designing Switches & Routers with APEX CAM | Altera |
41. | Apex |
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40 | APEX 20KE PCI Starter & Development Kits Data Sheet | Altera |
42. | Apex |
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8 | SignalTap Embedded Logic Analyzer Megafunction Data Sheet | Altera |
43. | Apex |
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2 | New APEX 20KE Device Ordering Codes | Altera |
44. | Apex |
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20 | Using APEX 20K & APEX 20KE PLLs in the Quartus Software | Altera |
45. | Apex |
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30 | Using LVDS in the Quartus Software | Altera |
46. | Apex |
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6 | Board Design Guidelines for LVDS Systems | Altera |
47. | Apex |
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8 | APEX II Devices | Altera |
48. | Apex |
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96 | APEX II Programmable Logic Device Family Data Sheets | Altera |
49. | Apex |
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8 | MasterBlaster Serial/USB Communications Cable Data Sheets | Altera |
50. | Apex 20K |
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4 | Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) | Altera |
51. | Apex 20K |
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102 | AN 116: Configuring SRAM-Based LUT Devices | Altera |
52. | Apex 20K |
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4 | Figure 43 Design File for Configuring APEX 20K (43 KB) | Altera |
53. | Apex 20K |
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50 | AN 119: Implementing High-Speed Search Applications with Altera CAM | Altera |
54. | Apex 20K |
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56 | AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices | Altera |
55. | Apex 20K |
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15 | AN 138: LVDS Signaling Using APEX Devices I/O Pins | Altera |
56. | Apex 20K |
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12 | AN 107: Using Altera Devices in Multi-Voltage Systems | Altera |
57. | Apex 20K |
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13 | AN 114: Designing with FineLine BGA Packages | Altera |
58. | Apex 20K |
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24 | AN 106: Designing with 2.5-V Devices | Altera |
59. | Apex 20K |
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30 | AN 117: Using Selectable I/O Standards in Altera Devices | Altera |
60. | Apex 20K |
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32 | EPC16 Configuration Device Data Sheet | Altera |
61. | Apex 20K |
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5 | Configuring PLDs with FLASH Memory | Altera |
62. | Apex 20K |
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116 | APEX 20K Programmable Logic Device Family Data Sheet | Altera |
63. | Apex 20K |
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90 | APEX 20KC Programmable Logic Device Data Sheet | Altera |
64. | Apex 20K |
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1 | EP20K400 Device | Altera |
65. | Apex 20K |
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3 | APEX 20KE Programmable Logic Devices | Altera |
66. | Apex 20K |
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8 | MasterBlaster Serial/USB Communications Cable Data Sheet | Altera |
67. | Apex 20K |
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28 | Configuration Devices for APEX & FLEX Devices Data Sheet | Altera |
68. | Apex 20K |
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16 | Quartus Programmable Logic Development System & Software Data Sheet | Altera |
69. | Apex 20K |
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4 | TB 56: Using APEX 20KE CAM for Fast Search Applications | Altera |
70. | Apex 20K |
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6 | TB 57: Power Consumption Comparison: APEX 20K vs. Virtex Devices | Altera |
71. | Apex 20K |
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4 | TB 60: Advantages of APEX PLLs over Virtex DLLs | Altera |
72. | Apex 20K |
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4 | TB 61: CAM Comparison: APEX 20KE vs. Virtex-E Devices | Altera |
73. | Apex 20K |
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7 | TB 70: Jitter Comparison Analysis APEX 20KE PLL vs. Virtex-E DLL | Altera |
74. | Apex 20K |
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8 | APEX CAM as Cache for External CAM | Altera |
75. | APEX CAM |
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6 | Designing Switches & Routers with APEX CAM White Paper | Altera |
76. | Apex II |
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4 | Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) | Altera |
77. | Apex II |
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102 | AN 116: Configuring SRAM-Based LUT Devices | Altera |
78. | Apex II |
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50 | AN 119: Implementing High-Speed Search Applications with Altera CAM | Altera |
79. | Apex II |
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10 | AN 162: Increasing System Bandwidth with CDS | Altera |
80. | Apex II |
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12 | ByteBlasterMV Parallel Port Download Cable Data Sheets | Altera |
81. | Application Brief |
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3 | AB 124: Prescaled Counters in FLEX 8000 Devices | Altera |
82. | Application Brief |
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3 | AB 130: Parity Generators in FLEX 8000 Devices | Altera |
83. | Application Brief |
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4 | AB 131: State Machine Encoding | Altera |
84. | Application Brief |
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4 | AB 135: Ripple-Carry Gray Code Counters in FLEX 8000 Devices | Altera |
85. | Application Brief |
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19 | AB 143: Understanding FLEX 8000 Timing | Altera |
86. | Application note |
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4 | Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) | Altera |
87. | Application note |
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102 | AN 116: Configuring SRAM-Based LUT Devices | Altera |
88. | Application note |
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4 | Figure 43 Design File for Configuring APEX 20K (43 KB) | Altera |
89. | Application note |
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50 | AN 119: Implementing High-Speed Search Applications with Altera CAM | Altera |
90. | Application note |
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56 | AN 115: Using the ClockLock & ClockBoost PLL Features in APEX Devices | Altera |
91. | Application note |
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15 | AN 138: LVDS Signaling Using APEX Devices I/O Pins | Altera |
92. | Application note |
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12 | AN 107: Using Altera Devices in Multi-Voltage Systems | Altera |
93. | Application note |
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13 | AN 114: Designing with FineLine BGA Packages | Altera |
94. | Application note |
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24 | AN 106: Designing with 2.5-V Devices | Altera |
95. | Application note |
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30 | AN 117: Using Selectable I/O Standards in Altera Devices | Altera |
96. | Application note |
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10 | AN 162: Increasing System Bandwidth with CDS | Altera |
97. | Application note |
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39 | AN 33: Configuring FLEX 8000 Devices | Altera |
98. | Application note |
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21 | AN 38: Configuring Multiple FLEX 8000 Devices | Altera |
99. | Application note |
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24 | AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor | Altera |
100. | Application note |
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31 | AN 91: Understanding FLEX 10K Timing | Altera |