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Xilinx 400 dokumentacji

NO. Symbol elementu Rozmiar pliku Stron Opis dokumentacji Producent
1. Application Note 40 KB 5 Loadable Binary Counters Xilinx
2. Application Note 54 KB 5 Register Based FIFO Xilinx
3. Application Note 81 KB 8 Boundary Scan Emulator for XC3000 Xilinx
4. Application Note 10 KB 2 Complex Digital Waveform Generator Xilinx
5. Application Note 25 KB 4 Harmonic Frequency Synthesizer and FSK Modulator Xilinx
6. Application Note 19 KB 2 Bus Structured Serial Input/Output Device Xilinx
7. Application Note 7 KB 1 LCA Speed Estimation: Asking the Right Question Xilinx
8. Application Note 19 KB 2 Quadrature Phase Detector Xilinx
9. Application Note 97 KB 10 Using the Dedicated Carry Logic in XC4000E Xilinx
10. Application Note 34 KB 4 Ultra-Fast Synchronous Counters Xilinx
11. Application Note 58 KB 8 Using the XC4000 Readback Capability Xilinx
12. Application Note 214 KB 17 Boundary Scan in XC4000/XC5200 Device Xilinx
13. Application Note 37 KB 4 Estimating the Performance of XC4000E Adders and Counters Xilinx
14. Application Note 64 KB 7 Adders, Subtracters and Accumulators in XC3000 Xilinx
15. Application Note 26 KB 4 Accelerating Loadable Counters in XC4000 Xilinx
16. Application Note 108 KB 11 XC3000 Series Technical Information Xilinx
17. Application Note 37 KB 6 Multiplexers and Barrel Shifters in XC3000 Series Xilinx
18. Application Note 30 KB 4 Implementing State Machines in FPGA Devices Xilinx
19. Application Note 34 KB 2 Frequency/Phase Comparator for Phase Locked Loops Xilinx
20. Application Note 32 KB 3 Serial Code Conversion between BCD and Binary Xilinx
21. Application Note 23 KB 3 Megabit FIFO in Two Chips: One LCA Device and One DRAM Xilinx
22. Application Note 161 KB 15 Improving XC4000 Design Performance Xilinx
23. Application Note 35 KB 4 XC4000 Series Technical Information Xilinx
24. Application Note 137 KB 12 Synchronous and Asynchronous FIFO Designs Xilinx
25. Application Note 113 KB 6 Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators Xilinx
26. Application Note 234 KB 16 Implementing FIFOs in XC4000 Series RAM Xilinx
27. Application Note 111 KB 8 Constant Coefficient Multipliers for the XC4000E Xilinx
28. Application Note 116 KB 10 Block Adaptive Filter Xilinx
29. Application Note 71 KB 8 System Design with New XC4000X I/O Features Xilinx
30. Application Note 213 KB 16 Using SelectRAM Memory in XC4000 Series FPGAs Xilinx
31. Application Note 589 KB 38 Xilinx In-System Programming Using an Embedded Microcontroller Xilinx
32. Application Note 78 KB 6 Gate Count Capacity Metrics for FPGAs Xilinx
33. Application Note 117 KB 10 Design Migration from XC4000 to XC5200 Xilinx
34. Application Note 71 KB 9 Design Migration from XC2000/XC3000 to XC5200 Xilinx
35. Application Note 63 KB 6 Design Migration from XC4000 to XC4000E Xilinx
36. Application Note 51 KB 4 XC4000 Series Edge-Triggered and Dual-Port RAM Capability Xilinx
37. Application Note 39 KB 6 Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools Xilinx
38. Application Note 13 KB 1 In-System Programming Times Xilinx
39. Application Note 121 KB 7 Using the XC9500 JTAG Boundary Scan Interface Xilinx
40. Application Note 41 KB 6 Using In-System Programmability in Boundary Scan Systems Xilinx
41. Application Note 46 KB 4 Using the XC9500 Timing Model Xilinx
42. Application Note 75 KB 8 Designing with XC9500 CPLDs Xilinx
43. Application Note 58 KB 5 Pin Preassigning with XC9500 CPLDs Xilinx
44. Application Note 38 KB 4 Embedded Instrumentation Using XC9500 CPLDs Xilinx
45. Application Note 40 KB 4 XC9536 ISP Demo Board Xilinx
46. Application Note 99 KB 8 Configuring Xilinx FPGAs Using an XC9500 CPLD and Parallel PROM Xilinx
47. Application Note 46 KB 4 Supply Voltage Migration, 5 V to 3.3 V Xilinx
48. Application Note 29 KB 2 I/O Characteristics of the 'XL FPGAs Xilinx
49. Application Note 63 KB 8 FPGA Configuration Guidelines Xilinx
50. Application Note 27 KB 2 Configuring Mixed FPGA Daisy Chains Xilinx
51. Application Note 38 KB 4 Configuration Issues: Power-up, Volatility, Security, Battery Back-up Xilinx
52. Application Note 34 KB 2 Dynamic Reconfiguration Xilinx
53. Application Note 27 KB 3 Metastable Recovery Xilinx
54. Application Note 12 KB 1 Set-up and Hold Times Xilinx
55. Application Note 8 KB 1 Overshoot and Undershoot Xilinx
56. Application Note 21 KB 2 Xilinx FPGAs: A Technical Overview for the First Time User Xilinx
57. Application Note 102 KB 9 The Low-Cost, Efficient Serial Configuration of Spartan FPGAs Xilinx
58. Application Note 37 KB 6 Choosing a Xilinx Product Family Xilinx
59. Application Note 81 KB 5 XC9500 Remote Field Upgrade Xilinx
60. Application Note 136 KB 8 The Tagalyzer - A JTAG Boundary Scan Debug Tool Xilinx
61. Application Note 26 KB 1 A Quick JTAG ISP Checklist Xilinx
62. Application Note 333 KB 28 A CPLD VHDL Introduction Xilinx
63. Application Note 250 KB 18 Synopsys/Xilinx High Density Design Methodology Using FPGA Compiler Xilinx
64. Application Note 164 KB 18 Chip-Level HDL Simulation Using the Xilinx Alliance Series Xilinx
65. Application Note 84 KB 14 Hints, Tips and Tricks for Using XABEL with Xilinx M1.5 Design and Implementation Tools Xilinx
66. Application Note 33 KB 3 XC9500 CPLD Power Sequencing Xilinx
67. Application Note 72 KB 8 Using the XC9500XL Timing Model Xilinx
68. Application Note 158 KB 9 Designing With XC9500XL CPLDs Xilinx
69. Application Note 37 KB 10 Faster Erase Times for XC95216 and XC95108 Devices on HP 3070 Series Testers Xilinx
70. Application Note 98 KB 5 Understanding XC9500XL CPLD Power Xilinx
71. Application Note 114 KB 8 Planning for High Speed XC9500XL Designs Xilinx
72. Application Note 52 KB 7 Adapting ASIC Designs for Use with Spartan FPGAs Xilinx
73. Application note 85 KB 6 How Spartan FPGAs -- The Gate Array Solution Xilinx
74. Application Note 139 KB 13 The Express Configuration of Spartan-XL FPGAs Xilinx
75. Application Note 46 KB 6 Using Three-State Enable Registers in XLA, XV, and Spartan-XL FPGAs Xilinx
76. Application Note 28 KB 3 Using Manual Power Down Mode With Spartan-XL FPGAs Xilinx
77. Application Note 21 KB 3 Conserving Power With Auto Power Down Mode in Spartan-XL FPGAs Xilinx
78. Application Note 84 KB 7 Data Generation and Configuration for Spartan Series FPGAs Xilinx
79. Application Note 95 KB 11 Using the Virtex Block SelectRAM+ Features Xilinx
80. Application Note 75 KB 6 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature Xilinx
81. Application Note 88 KB 15 Using the Virtex Delay-Locked Loop Xilinx
82. Application Note 230 KB 43 Using the Virtex SelectI/O Resource Xilinx
83. Application Note 103 KB 16 Virtex Synthesizable High Performance SDRAM Controller Xilinx
84. Application Note 25 KB 2 Virtex I/V Curves for Various Output Options Xilinx
85. Application Note 44 KB 6 Synthesizable 143 MHz ZBT SRAM Interface Xilinx
86. Application Note 93 KB 7 Configuring Virtex FPGAs from Parallel EPROMs with a CPLD Xilinx
87. Application Note 407 KB 39 Virtex Configuration and Readback Xilinx
88. Application Note 97 KB 15 Configuration and Readback of Virtex FPGAs Using (JTAG) Boundary-Scan Xilinx
89. Application Note 17 KB 1 In-System Programming Times for XC9500XL Xilinx
90. Application Note 64 KB 6 Designing CPLD Multi-voltage Systems Xilinx
91. Application note 57 KB 10 Designing an Eight Channel Digital VoltMeter with the Insight Springboard Kit Xilinx
92. Application note 550 KB 29 Low Power Handspring SpringboardModule Design with CoolRunner CPLDs Xilinx
93. Application note 130 KB 9 Designing an Oscilloscope with theInsight Springboard Kit Xilinx
94. Application Note 29 KB 2 I/V Curves for Various Device Families Xilinx
95. Application Note 248 KB 45 Virtex Series Configuration Architecture User Guide Xilinx
96. Application Note 49 KB 7 Virtex Power Estimator User Guide Xilinx
97. Application Note 181 KB 4 Status and Control Semaphore Registers Using Partial Reconfiguration Xilinx
98. Application Note 52 KB 8 Virtex Synthesizable Delta-Sigma DAC Xilinx
99. Application Note 47 KB 8 Virtex Analog to Digital Converter Xilinx
100. Application Note 1.76 MB 8 Board Routability Guidelines with Xilinx Fine-Pitch BGA Packages Xilinx

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