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Xilinx 400 dokumentacji
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NO. | Symbol elementu | Rozmiar pliku | Stron | Opis dokumentacji | Producent |
---|---|---|---|---|---|
101. | Application Note | 69 KB | 6 | Powering Virtex FPGAs | Xilinx |
102. | Application Note | 72 KB | 4 | XC1700 and XC18V00 Design Migration Considerations | Xilinx |
103. | Application Note | 49 KB | 7 | Using Xilinx and Synplify for Incremental Designing (ECO) | Xilinx |
104. | Application Note | 77 KB | 11 | Using Xilinx and Exemplar for Incremental Designing (ECO) | Xilinx |
105. | Application Note | 25 KB | 3 | TAU/BLAST Support in 2.1i | Xilinx |
106. | Application Note | 181 KB | 11 | Getting Started With the MultiLINX Cable | Xilinx |
107. | Application Note | 361 KB | 27 | MP3 NG: A Next Generation Consumer Platform | Xilinx |
108. | Application Note | 99 KB | 12 | Using Block SelectRAM+ Memory in Spartan-II FPGAs | Xilinx |
109. | Application Note | 110 KB | 13 | Using Delay-Locked Loops in Spartan-II FPGAs | Xilinx |
110. | Application Note | 56 KB | 4 | High Speed FIFOs In Spartan-II FPGAs | Xilinx |
111. | Application Note | 431 KB | 37 | Spartan-II FPGA Family Configuration and Readback | Xilinx |
112. | Application Note | 34 KB | 2 | Spartan-Family I/V Curves for Various Output Options | Xilinx |
113. | Application Note | 107 KB | 9 | Configuring Spartan-II FPGAs from Parallel EPROMs | Xilinx |
114. | Application Note | 313 KB | 21 | Using SelectI/O Interfaces in Spartan-II FPGAs | Xilinx |
115. | Application Note | 172 KB | 14 | SEU Mitigation Design Techniques for the XQR4000XL | Xilinx |
116. | Application Note | 162 KB | 16 | Configuration and Readback of Spartan-II FPGAs Using Boundary Scan | Xilinx |
117. | Application Note | 77 KB | 6 | Powering Xilinx Spartan-II FPGAs | Xilinx |
118. | Application Note | 98 KB | 6 | Interfacing a Virtex-E Device to a MIPS Processor | Xilinx |
119. | Application Note | 71 KB | 7 | Interfacing a Virtex-E Device to a Pentium Processor | Xilinx |
120. | Application note | 344 KB | 37 | Triple Module Redundancy DesignTechniques for Virtex FPGAs | Xilinx |
121. | Application Note | 164 KB | 16 | Synthesizable FPGA Interface for Retrieving ROM Number from 1-Wire Devices | Xilinx |
122. | Application Note | 273 KB | 23 | Writing Efficient Testbenches | Xilinx |
123. | Application Note | 103 KB | 15 | Virtex Synthesizable 1.6 Gbytes/s DDR SDRAM Controller | Xilinx |
124. | Application Note | 45 KB | 6 | An Overview of Multiple CAM Designs in Virtex Devices | Xilinx |
125. | Application Note | 140 KB | 12 | Content Addressable Memory (CAM) in ATM Applications | Xilinx |
126. | Application Note | 75 KB | 17 | Designing Flexible, Fast CAMs with Virtex Slices | Xilinx |
127. | Application Note | 101 KB | 19 | Using Block RAM for High-Performance Read/Write Cams | Xilinx |
128. | Application Note | 46 KB | 6 | Data-Width Conversion FIFOs Using the Virtex Block SelectRAM Memory | Xilinx |
129. | Application Note | 44 KB | 7 | An Inverse Discrete Cosine Transform (IDCT) Implementation in Virtex Devices for MPEG Video Applications | Xilinx |
130. | Application Note | 115 KB | 8 | IEEE 802.3 Cyclic Redundancy Check | Xilinx |
131. | Application Note | 86 KB | 5 | Linear Feedback Shift Registers in Virtex Devices | Xilinx |
132. | Application Note | 120 KB | 10 | PN Generators Using the SRL Macro | Xilinx |
133. | Application Note | 171 KB | 12 | CDMA Matched Filter Implementation in Virtex Devices | Xilinx |
134. | Application Note | 505 KB | 41 | 8-Bit Microcontroller for Virtex Devices | Xilinx |
135. | Application Note | 117 KB | 13 | Design Tips for HDL Implementation of Arithmetic Functions | Xilinx |
136. | Application Note | 107 KB | 12 | Correcting Single-Event Upsets Through Virtex Partial Configuration | Xilinx |
137. | Application Note | 125 KB | 9 | Gold Code Generators in Virtex Devices | Xilinx |
138. | Application Note | 167 KB | 13 | Transposed Form FIR Filters | Xilinx |
139. | Application Note | 135 KB | 10 | LFSRs as Functional Blocks in Wireless Applications | Xilinx |
140. | Application Note | 153 KB | 12 | 200 MHz UART with Internal 16-Byte Buffer | Xilinx |
141. | Application Note | 59 KB | 7 | Data Recovery in Virtex and Virtex-II Devices | Xilinx |
142. | Application Note | 47 KB | 8 | Data to Clock Phase Alignment | Xilinx |
143. | Application Note | 69 KB | 6 | The LVDS I/O Standard | Xilinx |
144. | Application Note | 82 KB | 11 | Multi-Drop LVDS with Virtex-E FPGAs | Xilinx |
145. | Application Note | 175 KB | 9 | Virtex-E LVDS Drivers & Receivers: Interface Guidelines | Xilinx |
146. | Application Note | 261 KB | 17 | Multi-Channel 622 Mb/s LVDS Data Transfer for Virtex-E Devices | Xilinx |
147. | Application Note | 91 KB | 14 | Virtex SelectLink Communications Channel | Xilinx |
148. | Application Note | 40 KB | 8 | Virtex Package Compatibility Guide | Xilinx |
149. | Application note | 95 KB | 8 | Virtex-E LVPECL Receivers in Multi-DropApplications | Xilinx |
150. | Application Note | 81 KB | 8 | LVDS System Data Framing | Xilinx |
151. | Application Note | 77 KB | 7 | High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices | Xilinx |
152. | Application Note | 44 KB | 6 | Virtex-EM FIR Filter for Video Applications | Xilinx |
153. | Application Note | 76 KB | 12 | Interfacing to Lara Networks Search Engine Using Virtex Devices | Xilinx |
154. | Application Note | 144 KB | 20 | Eight Channel, One Clock, One Frame LVDS Transmitter/Receiver | Xilinx |
155. | Application note | 164 KB | 16 | PowerPC 60X Bus Interface to a Virtex-EDevice | Xilinx |
156. | Application Note | 63 KB | 4 | Hot-Swapping Virtex-II Devices | Xilinx |
157. | Application note | 154 KB | 12 | Synthesizable 266 MBits/s DDR SDRAMController | Xilinx |
158. | Application Note | 119 KB | 17 | The Virtex-II SiberBridge | Xilinx |
159. | Application Note | 47 KB | 4 | FIFOs Using Virtex-II Shift Registers | Xilinx |
160. | Application Note | 77 KB | 6 | FIFOs Using Virtex-II Block RAM | Xilinx |
161. | Application note | 80 KB | 6 | Data-Width Conversion FIFOs Using theVirtex-II Block RAM Memory | Xilinx |
162. | Application Note | 79 KB | 6 | Quad Data Rate (QDR) SRAM Interface for | Xilinx |
163. | Application note | 146 KB | 13 | High-Speed Data Serialization andDeserialization (840 Mb/s LVDS) | Xilinx |
164. | Application note | 45 KB | 3 | Parity Generation and Validationin Virtex-II Devices | Xilinx |
165. | Application note | 148 KB | 12 | High-Speed DES and Triple DESEncryptor/Decryptor | Xilinx |
166. | Application Note | 105 KB | 9 | Color Space Converter | Xilinx |
167. | Application note | 72 KB | 4 | 3 x 3 Matrix Multiplier for3D Graphics and Video | Xilinx |
168. | Application note | 149 KB | 11 | Serial Digital Interface (SDI)Video Decoder | Xilinx |
169. | Application Note | 84 KB | 6 | Common Switch Interface CSIX-L1 Reference Design | Xilinx |
170. | Application Note | 59 KB | 4 | Self-Addressing FIFO | Xilinx |
171. | Application note | 159 KB | 12 | Serial Digital Interface (SDI) VideoEncoder | Xilinx |
172. | Application Note | 155 KB | 17 | In-System Programming (ISP) | Xilinx |
173. | Application Note | 42 KB | 4 | Power Up Reset Characteristics of CoolRunner CPLDs | Xilinx |
174. | Application Note | 59 KB | 6 | Five Volt Tolerance and PCI | Xilinx |
175. | Application Note | 70 KB | 8 | Differences In ABEL and PHDL | Xilinx |
176. | Application Note | 408 KB | 41 | Design of an MP3 Portable Player Using a CoolRunner CPLD | Xilinx |
177. | Application Note | 65 KB | 6 | Understanding True CMOS Outputs | Xilinx |
178. | Application Note | 78 KB | 6 | Pin Locking in CoolRunner XPLA3 CPLDs | Xilinx |
179. | Application Note | 168 KB | 19 | CoolRunner XPLA3 I | Xilinx |
180. | Application Note | 64 KB | 5 | Utilizing XPLA3 Universal Control Terms | Xilinx |
181. | Application Note | 100 KB | 8 | Macrocell Configurations in CoolRunner XPLA3 CPLDs | Xilinx |
182. | Application note | 274 KB | 26 | Design of a 16b/20b Encoder/DecoderUsing a CoolRunner CPLD | Xilinx |
183. | Application note | 274 KB | 26 | Design of a 16b/20b Encoder/DecoderUsing a CoolRunner CPLD | Xilinx |
184. | Application Note | 3.12 MB | 26 | Using Xilinx WebPACK and ModelTech ModelSim Xilinx Edition (MXE) | Xilinx |
185. | Application Note | 54 KB | 6 | Manchester Encoder-Decoder for Xilinx CPLDs | Xilinx |
186. | Application Note | 34 KB | 3 | UARTs in Xilinx CPLDs | Xilinx |
187. | Application Note | 57 KB | 6 | XPLA3 I/O Cell Characteristics | Xilinx |
188. | Application Note | 60 KB | 2 | In-System Programming of XPLA3 Devices | Xilinx |
189. | Application note | 132 KB | 11 | IrDA and UART Design in a CoolRunnerCPLD | Xilinx |
190. | Application Note | 278 KB | 11 | Low Power Tips for CoolRunner Design | Xilinx |
191. | Application Note | 81 KB | 9 | Decrease Processor Power Consumption Using a CoolRunner CPLD | Xilinx |
192. | Application note | 216 KB | 20 | CoolRunner XPLA3 Serial PeripheralInterface Master | Xilinx |
193. | Application note | 103 KB | 11 | CoolRunner CPLD 8051 MicrocontrollerInterface | Xilinx |
194. | Application note | 257 KB | 11 | Implementing HDL with WebPACK ECSSchematic Editor | Xilinx |
195. | Application note | 118 KB | 10 | Utilizing a User Constraint File for CoolRunner CPLDs | Xilinx |
196. | Application note | 175 KB | 20 | CoolRunner XPLA3 SMBus ControllerImplementation | Xilinx |
197. | Application note | 441 KB | 15 | Using Xilinx CPLDs to Interface to aNAND Flash Memory Device | Xilinx |
198. | Application note | 313 KB | 28 | Serial ADC Interface Using a CoolRunner CPLD | Xilinx |
199. | Application note | 110 KB | 10 | CoolRunner Visor Springboard LED Test | Xilinx |
200. | Application note | 37 KB | 3 | Understanding the Insight Springboard Development Kit | Xilinx |
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