Producenci
Altera 874 dokumentacji
| NO. | Symbol elementu | Rozmiar pliku | Stron | Opis dokumentacji | Producent |
|---|---|---|---|---|---|
| 401. | FLEX 10K |
226 KB |
20 | PIB 21: Implementing Logic with the Embedded Array in FLEX 10K Devices | Altera |
| 402. | FLEX 6000 |
37 KB |
4 | Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) | Altera |
| 403. | FLEX 6000 |
43 KB |
4 | Figure 43 Design File for Configuring APEX 20K (43 KB) | Altera |
| 404. | FLEX 6000 |
410 KB |
6 | Ordering Information | Altera |
| 405. | FLEX 6000 |
160 KB |
12 | AN 107: Using Altera Devices in Multi-Voltage Systems | Altera |
| 406. | FLEX 6000 |
212 KB |
13 | AN 114: Designing with FineLine BGA Packages | Altera |
| 407. | FLEX 6000 |
381 KB |
28 | Configuration Devices for APEX & FLEX Devices Data Sheet | Altera |
| 408. | FLEX 6000 |
515 KB |
12 | ByteBlasterMV Parallel Port Download Cable Data Sheets | Altera |
| 409. | FLEX 6000 |
273 KB |
14 | AN 90: SameFrame Pin-Out Design for FineLine BGA Packages | Altera |
| 410. | FLEX 6000 |
354 KB |
16 | ByteBlaster Parallel Port Download Cable Data Sheet | Altera |
| 411. | FLEX 6000 |
116 KB |
12 | Altera Programming Hardware Data Sheet | Altera |
| 412. | FLEX 6000 |
180 KB |
8 | MasterBlaster Serial/USB Communications Cable Data Sheet | Altera |
| 413. | FLEX 6000 |
2.42 MB |
69 | Altera Device Package Information Data Sheet | Altera |
| 414. | FLEX 6000 |
253 KB |
13 | Operating Requirements for Altera Devices Data Sheet | Altera |
| 415. | FLEX 6000 |
1.02 MB |
59 | FLEX 6000 Programmable Logic Device Family Data Sheet | Altera |
| 416. | FLEX 6000 |
399 KB |
17 | QFP Carrier & Development Socket Data Sheet | Altera |
| 417. | Functional Specification |
154 KB |
8 | FS 3: Integer Dividers | Altera |
| 418. | Functional Specification |
200 KB |
4 | FS 5: round Data Word Rounder | Altera |
| 419. | Functional Specification |
221 KB |
4 | FS 6: saturate Data Word Saturator | Altera |
| 420. | Functional Specification |
234 KB |
9 | FS 13: Atlantic Interface | Altera |
| 421. | Functional Specification |
278 KB |
24 | FS 12: pci_mt32 MegaCore Function Reference Design | Altera |
| 422. | Functional Specification |
208 KB |
10 | FS 8: Midbus Interface | Altera |
| 423. | Functional Specification |
522 KB |
8 | FS 9: AIRbus Interface | Altera |
| 424. | Functional Specification |
553 KB |
28 | FS 10: pci_mt64 MegaCore Function | Altera |
| 425. | Information |
216 KB |
12 | PIB 18: CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic | Altera |
| 426. | Information |
204 KB |
5 | PIB 26: Concurrent Programming through the JTAG Interface for MAX Devices | Altera |
| 427. | IP Megafunctions |
410 KB |
6 | Ordering Information | Altera |
| 428. | IP Megafunctions |
378 KB |
9 | AN 125: Evaluating AMPP & MegaCore Functions Application Notes | Altera |
| 429. | IP Megafunctions |
153 KB |
8 | Introducing MegaCore Functions Data Sheet | Altera |
| 430. | IP Megafunctions |
528 KB |
16 | Intellectual Property Selector Guide | Altera |
| 431. | IP Megafunctions |
86 KB |
2 | TB 25: Using the OpenCore Evaluation Feature Technical Brief | Altera |
| 432. | IP Megafunctions |
107 KB |
5 | Building Blocks for Rapid Communcation System Development White Paper | Altera |
| 433. | LVDS |
190 KB |
6 | Board Design Guidelines for LVDS Systems | Altera |
| 434. | Manual |
227 KB |
15 | AN 78: Understanding MAX 5000 & Classic Timing | Altera |
| 435. | Manual |
680 KB |
50 | Quartus II Installation & Licensing for UNIX Workstations Manual | Altera |
| 436. | Manual |
37.59 MB |
20 | Nios Embedded Processor Development Board Manual | Altera |
| 437. | Manual |
1.86 MB |
122 | Nios Embedded Processor Programmer's Reference Manual | Altera |
| 438. | Manual |
1.12 MB |
72 | Nios Embedded Processor Software Development Reference Manual | Altera |
| 439. | Manual |
613 KB |
43 | Quartus II Installation & Licensing for PCs Manual | Altera |
| 440. | Manual |
4.95 MB |
380 | MAX+PLUS II Getting Started Manual | Altera |
| 441. | Manual |
1.56 MB |
98 | Preface & Section 1: MAX+PLUS II Installation | Altera |
| 442. | Manual |
1.40 MB |
82 | Section 2: MAX+PLUS II - A Perspective | Altera |
| 443. | Manual |
2.03 MB |
122 | Section 3: MAX+PLUS II Tutorial | Altera |
| 444. | Manual |
1.16 MB |
77 | Appendices, Glossary & Index | Altera |
| 445. | Mature |
195 KB |
14 | AN 43: Designing for MAX 9000 Devices | Altera |
| 446. | Mature |
165 KB |
8 | AN 49: Implementing CRCC's In Altera Devices | Altera |
| 447. | Mature |
693 KB |
42 | Classic EPLD | Altera |
| 448. | Mature |
603 KB |
41 | MAX 9000 Programmable Logic Device Family Data Sheet | Altera |
| 449. | Mature de |
410 KB |
6 | Ordering Information | Altera |
| 450. | Mature devices |
160 KB |
12 | AN 107: Using Altera Devices in Multi-Voltage Systems | Altera |
| 451. | Mature devices |
381 KB |
28 | Configuration Devices for APEX & FLEX Devices Data Sheet | Altera |
| 452. | Mature devices |
144 KB |
3 | AB 124: Prescaled Counters in FLEX 8000 Devices | Altera |
| 453. | Mature devices |
174 KB |
3 | AB 130: Parity Generators in FLEX 8000 Devices | Altera |
| 454. | Mature devices |
109 KB |
4 | AB 131: State Machine Encoding | Altera |
| 455. | Mature devices |
185 KB |
4 | AB 135: Ripple-Carry Gray Code Counters in FLEX 8000 Devices | Altera |
| 456. | Mature devices |
96 KB |
19 | AB 143: Understanding FLEX 8000 Timing | Altera |
| 457. | Mature devices |
399 KB |
39 | AN 33: Configuring FLEX 8000 Devices | Altera |
| 458. | Mature devices |
439 KB |
21 | AN 38: Configuring Multiple FLEX 8000 Devices | Altera |
| 459. | Mature devices |
469 KB |
24 | AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor | Altera |
| 460. | Mature devices |
325 KB |
29 | AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices | Altera |
| 461. | Mature devices |
312 KB |
12 | AN 51: Using Programmable Logic for Gate Array Designs | Altera |
| 462. | Mature devices |
202 KB |
24 | AN 73: Implementing FIR Filters in FLEX Devices | Altera |
| 463. | Mature devices |
150 KB |
8 | AN 80: Selecting Sockets for Altera Devices | Altera |
| 464. | Mature devices |
512 KB |
12 | AN 74: Evaluating Power for Altera Devices | Altera |
| 465. | Mature devices |
118 KB |
8 | AN 81: Reflow Soldering Guidelines for Surface-Mount Devices | Altera |
| 466. | Mature devices |
224 KB |
11 | AN 36: Designing with FLEX 8000 Devices | Altera |
| 467. | Mature devices |
166 KB |
10 | AN 42: Metastability in Altera Devices | Altera |
| 468. | Mature devices |
261 KB |
15 | AN 75: High-Speed Board Designs 3.01 | Altera |
| 469. | Mature devices |
204 KB |
21 | AN 76: Understanding FLEX 8000 Timing | Altera |
| 470. | Mature devices |
237 KB |
18 | AN 77: Understanding MAX 9000 Timing | Altera |
| 471. | Mature devices |
227 KB |
15 | AN 78: Understanding MAX 5000 & Classic Timing | Altera |
| 472. | Mature devices |
196 KB |
11 | AN 85 In-System Programming Times for MAX Devices | Altera |
| 473. | Mature devices |
210 KB |
12 | AN 109: Using the HP 3070 Tester for In-System Programming | Altera |
| 474. | Mature devices |
116 KB |
12 | Altera Programming Hardware Data Sheet | Altera |
| 475. | Mature devices |
2.42 MB |
69 | Altera Device Package Information Data Sheet | Altera |
| 476. | Mature devices |
253 KB |
13 | Operating Requirements for Altera Devices Data Sheet | Altera |
| 477. | Mature devices |
283 KB |
16 | a16450 Universal Asynchronous Receiver/Transmitter Data Sheet | Altera |
| 478. | Mature devices |
243 KB |
8 | a6402 Universal Asynchronous Receiver/Transmitter Data Sheet | Altera |
| 479. | Mature devices |
270 KB |
22 | a8237 Programmable DMA Controller Data Sheet | Altera |
| 480. | Mature devices |
339 KB |
21 | a8251 Programmable Communications Interface Data Sheet | Altera |
| 481. | Mature devices |
412 KB |
16 | EP220 & EP224 Classic EPLDs Data Sheet | Altera |
| 482. | Mature devices |
492 KB |
18 | EP312 & EP324 Classic EPLDs Data Sheet | Altera |
| 483. | Mature devices |
1.05 MB |
63 | FLEX 8000 Programmable Logic Device Family Data Sheet | Altera |
| 484. | Mature devices |
221 KB |
24 | a8259 Programmable Interrupt Controller Data Sheet | Altera |
| 485. | Mature devices |
104 KB |
4 | MPLDs: Mask-Programmed Logic Devices Data Sheet | Altera |
| 486. | Mature devices |
58 KB |
4 | SB 5: Numerically Controlled Oscillator Megafunction | Altera |
| 487. | Mature devices |
203 KB |
4 | SB 18: Binary Pattern Correlator Megafunction | Altera |
| 488. | Mature devices |
150 KB |
4 | SB 25: PCI Bus Target Interface Megafunction | Altera |
| 489. | Mature devices |
154 KB |
8 | FS 3: Integer Dividers | Altera |
| 490. | Mature devices |
201 KB |
11 | AN 95: In-System Programmability in MAX Devices | Altera |
| 491. | MAX |
196 KB |
11 | AN 85: In-System Programming Times for MAX Devices | Altera |
| 492. | MAX |
253 KB |
13 | BitBlaster Serial Download Cable Data Sheet | Altera |
| 493. | MAX |
1.17 MB |
62 | MAX 7000 Programmable Logic Device Family Data Sheet, | Altera |
| 494. | MAX |
1.12 MB |
62 | MAX 7000B Programmable Logic Device Family Data Sheet | Altera |
| 495. | MAX |
35 KB |
2 | TB 33: Evaluating MAX 7000S Device Utilization and Fitting | Altera |
| 496. | MAX 3000 |
37 KB |
4 | Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) | Altera |
| 497. | MAX 3000 |
1.00 MB |
102 | AN 116: Configuring SRAM-Based LUT Devices | Altera |
| 498. | MAX 3000 |
43 KB |
4 | Figure 43 Design File for Configuring APEX 20K (43 KB) | Altera |
| 499. | MAX 3000 |
410 KB |
6 | Ordering Information | Altera |
| 500. | MAX 3000 |
160 KB |
12 | AN 107: Using Altera Devices in Multi-Voltage Systems | Altera |

226 KB